
`include "common_header.verilog"

//  *************************************************************************
//   File : lfsr2step.v
//  *************************************************************************
//  This program is controlled by a written license agreement.
//  Unauthorized Reproduction or Use is Expressly Prohibited. 
//  Copyright (c) 2005 Morethanip GmbH
//  info@morethanip.com
//  *************************************************************************
//  Version: $Id: lfsr2step.v,v 1.3 2006/06/16 15:55:50 mr Exp $ 
//  Author : Muhammad Anisur Rahman
//  *************************************************************************
//   Description:
// 
//   Random Integer generator with linear feed back shift register 
//   (lfsr) with two steps per clock cycle
// 
//  *************************************************************************

module lfsr2step (

   reset,
   clk,
`ifdef USE_CLK_ENA
   clk_ena,
`endif    
   lsb,
   x_lsb);
   
input   reset;          //  active high
input   clk;            //  156.25MHz Clock
`ifdef USE_CLK_ENA
input   clk_ena;
`endif
output  [1:0] lsb;      //  r used as code selector between |R| or |K|
output  [3:0] x_lsb;    //  these LSB 4 bits are loaded to the down counter

wire    [1:0] lsb; 
wire    [3:0] x_lsb; 
reg     [6:0] x_poli; //  coeffients for the 8th order polinomial

always @(posedge clk or posedge reset)
   begin : process_1
   if (reset == 1'b 1)
      begin
      x_poli <= {7{1'b 1}};   //  All registers are reseted to 1
      end
   else
      begin
        `ifdef USE_CLK_ENA
        if(clk_ena == 1'b 1)
        begin
        `endif
   // ------------------------------------------ //
   // flip flops work on rising clock edge       //
   // shifting all bits by 2 bit from MSB to LSB //
   // ------------------------------------------ //

        x_poli[0] <= x_poli[2];	
        x_poli[1] <= x_poli[3];	
        x_poli[2] <= x_poli[4];	
        x_poli[3] <= x_poli[5];	
        x_poli[4] <= x_poli[6];	
        x_poli[5] <= x_poli[1] ^ x_poli[0];	
        x_poli[6] <= x_poli[2] ^ x_poli[1];	
        `ifdef USE_CLK_ENA
        end
        `endif
      end
   end

assign lsb[0] = x_poli[0]; 
assign lsb[1] = x_poli[1]; 
assign x_lsb = x_poli[3:0]; 
   
endmodule // module lfsr2step